Rapidus 2nm 2HP Process Matches TSMC N2, Surpasses Intel 18A in Density

Japan’s semiconductor ambitions are taking shape at an astonishing pace, with Rapidus unveiling details of its upcoming 2nm manufacturing process, code-named 2HP. For months, industry watchers speculated whether Rapidus could truly compete with giants like TSMC and Intel.

Now, with newly reported logic density figures, the Japanese newcomer is positioning itself as a legitimate contender in advanced chipmaking.

According to data circulating in technical circles, Rapidus’ 2HP process achieves a logic density of 237.31 MTr/mm². This figure essentially puts it neck-and-neck with TSMC’s much-publicized N2 node, currently estimated at 236.17 MTr/mm². What makes the news even more remarkable is that Rapidus’ density numbers surpass Intel’s upcoming 18A node by a substantial margin. Intel’s design, despite its competitive performance metrics, is projected at just 184.21 MTr/mm² in logic density benchmarks.

Why does this matter? Logic density, the measure of how many transistors can be packed into a given space, directly influences the performance, power efficiency, and cost of processors. By rivaling TSMC and surpassing Intel in this metric, Rapidus signals that its 2HP process is not just a domestic achievement for Japan but also a potential global disruptor in chip technology.

Industry insiders explain that Rapidus achieved this parity using a High Density (HD) library with a cell height of 138 units on a G45 pitch. Both TSMC’s N2 and Rapidus’ 2HP appear to embrace this HD-cell design philosophy, prioritizing maximum transistor density. Intel’s approach differs: while its 18A relies on advanced features like backside power delivery (BSPDN), those innovations also occupy some of the front-side metal layers, reducing apparent density. Intel has made clear its main goal is not density but performance per watt, particularly since 18A is largely geared toward internal products and key partnerships.

What makes Rapidus particularly interesting is not just the numbers but its unique single-wafer front-end processing strategy. Instead of immediately focusing on massive production, the company fine-tunes smaller volumes first, then scales improvements outward. This agile, iterative approach could allow Rapidus to adapt faster than traditional manufacturing powerhouses, especially in a field where every nanometer matters.

Momentum is clearly on Rapidus’ side. Beyond its technological promises, the company has gained attention because it represents Japan’s renewed push to reassert itself in a semiconductor industry dominated by Taiwan, South Korea, and the United States. Partnerships and interest from major global players, including reports of NVIDIA’s attention, highlight that Rapidus is not a fringe experiment but a serious candidate to diversify the supply chain in an industry strained by geopolitics and surging demand.

Looking ahead, Rapidus has confirmed that its 2nm PDK (Process Design Kit) will be available to customers in early 2026. While that still places it behind TSMC’s planned N2 rollout, the density parity suggests customers may have a new and highly competitive option once the node is ready. For a market often accused of lacking meaningful competition at the bleeding edge, Rapidus’ entry could be a turning point.

Ultimately, whether 2HP lives up to expectations will depend on more than density. Yield, performance, power, and cost per transistor will all come under scrutiny. But one thing is clear: Rapidus has forced its way into the conversation, and that alone is a dramatic shift in the semiconductor landscape.